In order to save costs, such as wiring or interconnection costs, it is desirable to transmit digital data between remote sites in a serial manner. This allows a single optical fiber or wire (for example, coaxial or twisted-pair) to carry a serial stream of data bits. One such system of transmitting data is know as Fibre Channel. Two standards that have been implemented for Fibre Channel are the American National Standards Institute (ANSI) standard and the Gigabit Ethernet standard. The ANSI standard uses a frequency of 1.0625 GHz. The Gigabit Ethernet standard, however, uses a frequency of 1.25 GHz.
In order to further reduce costs, the clock data needed by a remote receiver to reclock the serial bit stream is often encoded with other data. The circuitry by which the clock data is recovered from the data stream is often called a clock recovery circuit. In some applications, it is desirable to recover the clock data and then reclock the data and send it serially to another location. The reclocking process reduces timing jitter on the encoded data, which typically results from transmitting serial data at high frequencies over various media. Reduction of jitter makes it possible for the clock recovery circuitry positioned downstream in the system to recover the data with a smaller probability of error. Thus, clock recovery is an important feature in digital communications.
Quite often it is desirable for a circuit to be able to convert parallel data into serial data and transmit the serial data via a transmission media using its own reference frequency. It is also advantageous to be able to receive data at the same time from a source that is not synchronized with a local source. The problem encountered when both functions need to be performed in the same circuit is that two frequencies that are close to each other--often within a few parts per million--must be generated.
If both clocks are to be generated using different circuitry, two VCOs running at nearly the same frequency are likely to be used. These two VCOs would be controlled by two different phase locked loops. An arrangement for generating these town frequencies is shown in FIGS. 1A and 1B.
As seen in FIG. 1A, a phase locked loop generates and independent transmit frequency (i.e., Transmit Clock) using a crystal or externally supplied reference clock. The reference frequency produced by the crystal or externally supplied reference clock is normally at a much lower frequency than the VCO frequency. For example, if the ANSI standard is used, the transmission frequency needs to be 1.0625 GHz an if the Gigabit Ethernet standard is used, the transmission frequency needs to be 1.25 GHz. The crystal or externally supplied reference clock, however, would have a frequency of 21.25 MHz if the ANSI standard were used and 25 MHz if the Gigabit Ethernet standard were used.
In the phase locked loop shown in FIG. 1A, the reference frequency produced by the crystal or externally supplied reference clock is compared via phase/frequency detector 102 to a divided down version of the much higher frequency generated VCO 106. The VCO frequency is divided down to an appropriate level via frequency divider 108. If a 25 MHz reference frequency is used in a Gigabit Ethernet system operating at 1.25 GHz, frequency divider 108 would have to divide the VCO frequency by 50.
Phase/frequency detector 102 compares the phases of the two low frequencies. The output of phase/frequency detector 12 drives loop filter 104, which includes a charge pump. The output of loop filter 104 controls VCO 106 thereby generating the correct transmit clock frequency.
As seen in FIG. 1B, the frequency for reclocking and data detection can be generated in a similar manner. In this feedback loop, however, the reference frequency can be extracted from the data stream or from the crystal or externally supplied reference clock. One was to achieve this extraction is to compare the data stream with the frequency produced by VCO 116.
To initially acquire a frequency, the VCO first locks to the externally supplied reference frequency generated by the crystal or externally supplied reference clock--much in the same was as discussed above with respect to FIG 1A. After the frequency of VCO 116 is close to the externally supplied reference frequency, multiplexer 110 causes the phase locked loop to switch over and begin using the data as the reference frequency instead of the crystal or the externally supplied reference clock. Once at the appropriate frequency, the output of VCO 116 is used to reclock the data via flip flop 120.
There are problems that are often encountered when using the foregoing approach. For example, injection locking of VCOs 106 and 116 can occur. This is caused by noise coupling between VCOs 106 and 116 through the power supply and ground lines or through the substrate. More particularly, injection locking means that while the two frequencies produced by VCOs 106 and 116 are suppose to slowly shift past each other in phase, at some point in the phase relationship, the two phases tend to lock together for a short while and then slip apart thereby causing excessive jitter.
In order to overcome this problem a hybrid approach such as the one shown in FIG. 2 has been used. In this design, analog and digital techniques have been combined and only one VCO 202 is required. The asynchronous data recovery clock is generated by first locking VCO 202 to an external crystal or other reference frequency. In the implementation shown in FIG. 2, VCO 202 is implemented in such a way as to have available, simultaneously, multiple phases. For example, VCO 202 can be a voltage controlled ring oscillator with 5 differential stages thereby producing 10 different phases simultaneously. The recovered clock frequency is selected from one of the 10 phases by multiplexer 206. The selected recovered clock frequency and the data stream are compared in up/down detector 208. A phase higher or lower then the presently selected phase is selected in accordance with an "up" or a "down" signal generated by up/down detector 208 after filtering is performed by digital loop filter 210.
In digital loop filter 210, the up and down pulses are used to shift a single bit back and forth in a high speed left/right shift register. When the bit reaches one end of the shift register, the next phase of ring oscillator 202 is selected by multiplexer 206.
The problem with the forgoing design is that the recovered clock phase is limited to being one of the few phases generated by VCO 202. In order to ensure a low amount of jitter, the differences between the phases generated by VCO 202 must be small. Thus, this design requires a VCO with numerous stages so as to generate small phase steps. In other words, the more stages the VCO has the smaller the steps are between stages. At high frequencies, however, it is difficult to generate a ring oscillators with a large number of stages. For example, if a frequency of 1.0625 GHz with 32 different phase selections were desired, the ring oscillator would have to contain 16 stages with each stage having a propagation delay of only 58.8 ps (i.e., (1/1.0625 GHz)/16). In addition, the 16 outputs from the ring oscillator would have to be routed to multiplexer 206, which would have to be able to switch between these outputs without adversely affecting the clock frequency. Further, the routing of the output lines and the multiplexing would have to maintain the 58.8 ps timing resolution. These high speed requirements would require a large amount of power dissipation and are incompatible with current commercial semiconductor processes.